Verilog: Posedge sensitivity vs. If statement in Always block

by douglas.yamamoto   Last Updated September 11, 2019 16:25 PM

I have recently completed a design that had run into timing issues (negative slack). The modules that were found to be troublesome, from the timing reports generated in Vivado 2017.4, are these modules that are used to calculate some synchronous outputs. A clock, reset, and enable (en) signal are provided as inputs. The modules that had these issues were previously implemented as shown below:

always @ (clk, rst) begin if (rst) begin ... ... end else if (clk & en) begin ... ... end end

A coworker suggested that the "code is creating latches for the pipeline segments, instead of clocked flip flops". Following his suggestions I changed the modules to what is shown below.

always @ (posedge clk, posedge rst) begin
     if (rst) begin
          ...
          ...
     end
     else if (en) begin
          ...
          ...
     end
end

This seems to have resolved the negative slack coming from these modules, but I am curious to know why this is the case.



Answers 1


A coworker suggested that the "code is creating latches for the pipeline segments, instead of clocked flip flops".

You co-worker is wrong. In fact the first circuit can not be translated to hardware at all as there are no logic components which 'work' on both (rising and falling) clock or reset edges.
If your try to synthesis you will get some sort of error like "Can't map logic on hardware" or "No target logic exist".

It can only be used in behavioral code.

Oldfart
Oldfart
September 11, 2019 16:22 PM

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