I want to use FSMC of STM32F429 to read external FIFO implemented in an FPGA MAX10. Since no mode of FSMC can fit the FIFO interface precisely, I try to use the modified synchronous multiplexed PSRAM mode.
My plan is like this
A[25:16]: Ignored, don't connect to FIFO;
NEx, NOE, NADV: Implement a simple logic in FPGA that when NEx is valid and the NADV is data valid, connect the inverted NOE to the RD port of FIFO;
NWE: ignored, only read operation is needed;
D[15:0]: Connect to the output data port of FIFO;
There may be also some logic in FPGA to adjust the timing between NOE and D[15:0], but that is not a big problem.
My questions are: