Output on Pass-transistor NAND gate lower than expected

by Vinh Trung Thai   Last Updated October 09, 2019 18:25 PM

I have an assignment to design an IC NAND gate, consisting og 2 NMOS-transistors and a designed inverter as seen in figure 1 and 2.

But when measuring the output at Vout, we only get about 60% of the expected value, which would be 1.5V. I can't figure out the issue

Settings:

VDD = 1.5V

Vin_A:

  • Amplitude = 0 - 1.5 V
  • Period = 2 ns
  • Rise Time = 0.1 ns
  • Fall Time = 0.1 ns
  • Pulse Width = 1 ns
  • Delay = 0 ns

Vin_B:

  • Amplitude = 0 - 1.5 V
  • Period = 2 ns
  • Rise Time = 0.1 ns
  • Fall Time = 0.1 ns
  • Pulse Width = 1 ns
  • Delay = 0.5 ns

Figures

enter image description here [Figure 1]

enter image description here [Figure 2]

enter image description here [Figure 3]



Answers 1


Remember that for an NMOS transistor to conduct you must bring the gate voltage above the source voltage, and we usually expect the difference to be at least equal to the transistor's threshold voltage if want significant current.

The sources of your two NMOS transistors are connected to the NAND gate output, so the NAND gate output (the sources) must be at a lower voltage than the transistor gates when the transistors are conducting. If the highest voltage in your circuit is 1.5V, and you drive the transistor gates to 1.5V, then the NMOS transistors can not bring the NAND output voltage any higher than (approximately) \$1.5\,\mathrm{V}-V_{THN}\$

Elliot Alderson
Elliot Alderson
October 09, 2019 17:37 PM

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